Advanced computer architectures may employ multiple microprocessors. Some advanced computer architectures may employ multiple microprocessors on one silicon chip. In a typical application, two microprocessors may be implemented on a single silicon chip, and the implementation may be referred to as a dual core processor. Two or more of the multiple microprocessors may operate in a lock step mode, meaning that each of the lock stepped microprocessors process the same code sequences, and should, therefore, produce identical outputs. FIG. 1A illustrates a typical implementation of a dual core processor. A dual core processor 10 includes a silicon chip 11 having microprocessor core 12 (core 0) and microprocessor core 14 (core 1). The microprocessor cores 12 and 14 are coupled to an interface logic 16 that monitors external communications from the microprocessor cores 12 and 14. In the dual core processor 10, the microprocessor cores 12 and 14 operate as independent entities. While the dual core processor 10 has advantages in terms of size and processing speed, the reliability of the dual core processor 10 is not significantly better than that of two single core processors.
To enhance reliability, the dual core processor, or other multiple microprocessor architected computer systems, may employ lock step features. FIG. 1B is a diagram of a prior art dual core processor that uses lock step techniques to improve overall reliability. In FIG. 1B, a computer system 18 includes a dual core processor 20 having a single silicon chip 21, on which are implemented microprocessor core 22 and microprocessor core 24. To employ lock step, each of the microprocessor cores 22 and 24 process the same code streams. To ensure reliable operation of the dual core processor 20, each of the microprocessors 22 and 24 may operate in “lock step.” An event that causes a loss of lock step can occur on either or both of the microprocessor cores 22 and 24. An example of such an event is a data cache error. A loss of lock step, if not promptly corrected, may cause the computer system 18 to “crash.” That is, a failure of one microprocessor core may halt processing of the dual core processor 20, and the computer system I 18, even if the other microprocessor core does not encounter an error.
To detect a loss of lock step, a lock step logic 26, which may be external to the chip 21, compares outputs from the microprocessor cores 22 and 24. A difference in processing detected by the lock step logic 26 is by definition a loss of lock step. A drawback to the dual core processor architecture shown in FIG. 1B is that the logic to determine loss of lock step is external to the chip. This configuration imposes delays in determining loss of lock step, and requires additional architectural features.
The dual core processor 20 also makes recovery from a loss of lock step difficult and time-consuming. FIG. 1C illustrates a current methodology for recovering from a loss of lock step. In FIG. 1C, the dual core processor 20 is shown coupled to memory 25. Should the dual core processor 20 suffer a loss of lock step, recovery may be initiated by the memory 25 saving the architected state of one of the microprocessors 22 and 24 (i.e., the microprocessor that is considered “good”). Then, both microprocessors 22 and 24 are reset and reinitialized. Finally, the architected states of each of the microprocessors 22 and 24 is copied from the memory 25 into the microprocessors 22 and 24, respectively. This prior art methodology for recovery from a loss of lock step makes the microprocessors 22 and 24 unavailable for an amount of time. If the amount of time required for recovery is too long, the computer system 18 employing the dual core processor 20 may “crash.”